(a) Field of the Invention
The present invention relates to a semiconductor device including a signal generator which delivers a fixed output signal in a specific mode, and is activated upon occurring of a timing signal to change the output signal thereof.
(b) Description of the Related Art
Some semiconductor devices include a signal generator which operates upon occurring of a timing signal and does not deliver an active output during a period other than the period of occurring of the timing signal. Examples of such a signal generator include a test-mode signal generator which outputs a test mode signal for starting a test mode of the semiconductor device. In general, an ordinary signal line in a semiconductor device experiences a signal transition thereon along with a normal operation of a circuit component of the semiconductor device. On the other hand, the test mode signal output from the test-mode signal generator is irrelevant to the normal operation, and does not change the level thereof in the normal operation.
A normal signal line, which is active during the normal operation mode of the semiconductor device, is generally made of a low resistance material such as aluminum. On the other hand, a specific signal line, which is inactive in the normal operation mode, such as a test-mode signal line, is often made of a high resistance material such as tungsten. The specific signal line e.g., test-mode signal line may extend in a long distance between the mode-signal generation circuit and a signal receiving circuit such as a test execution circuit. The configuration wherein the specific signal line such as a test-mode signal line is made of the high resistive material is described in Patent Publications JP-1999-163065A and -1994-177251A, for example.
FIG. 3 shows a known semiconductor device including the test-mode signal generator. In this figure, a portion of the semiconductor device is expressed by an equivalent circuit including a coupling capacitance between the test-mode signal line and the normal signal line. A mode decode/latch circuit 201 decodes a code (command) input through an external signal terminal IAi for instructing start of a test mode. The mode decode/latch circuit 201 decodes the input command based on a latch timing signal TMRS occurring at the test mode, and generates a test-mode signal TEST1 based on the contents thus decoded. A signal line 204 is a normal signal line irrelevant to the test mode signal, and in this example, transmits a normal signal /SIG1, which is generated in a buffer 205 by reversing a normal signal SIG1.
A test execution circuit 202 receives the test-mode signal TEST1 output from the mode decode/latch circuit 201 and is controlled thereby. The test-mode signal TEST1 is received by a buffer 206, which outputs a test mode signal /TEST1 after reversing the test-mode signal TEST1, and is used in the test execution circuit 202. A test-mode signal line (TEST1 signal line) 203 for transmitting the test-mode signal TEST1 extends over a long distance from the mode decode/latch circuit 201 to the test execution circuit 202, which is controlled by the test-mode signal TEST1 to execute the test operation of the semiconductor device. The test-mode signal line 203 includes a first portion 203a which is made of a high-resistance material, such as tungsten, and extends over a long distance extending from the mode decode/latch circuit 201 to the vicinity of the test execution circuit 202, and a second portion 203b which is made of a low-resistance material, such as aluminum, and connects the distal end of the first portion 203a to the input of the test execution circuit 202.
Since the TEST1 signal line 203 has a higher resistance, the TEST1 signal line 203 is susceptive to a transition noise occurring on an adjacent signal line. If a normal signal line such as /SIG1 normal signal line 204 is disposed adjacent to the first portion 203a or second portion 203b of the TEST1 signal line 203, the TEST1 signal line 203 receives a transition noise from the adjacent /SIG1 normal signal line 204 upon a transition of the signal thereon and is affected by the transition noise to have a significant potential fluctuation.
FIG. 4 shows the waveform of the above situation in the semiconductor device 200 shown in FIG. 3. In the example of FIG. 3, the test-mode signals TEST1 and /TEST1 are fixed at L-level and H-level, respectively, to maintain the semiconductor device 200 in a normal mode before occurring of a signal transition of the normal signal /SIG1. When the normal signal /SIG1 rises to an H-level during the normal operation mode, the test-mode signal line 203 is affected by the signal transition of the adjacent /SIG1 normal signal line 204 in the vicinity of the distal end, i.e., node N21, of the test-mode signal line 203 due to a capacitive coupling. This causes a potential fluctuation of the test-mode signal TEST1, and if the range of potential fluctuation is large enough to cause a logical inversion of the test-mode signal TEST1 from an L-level to an H-level, as shown by a left dotted circle in FIG. 4, the test execution circuit 202 interprets the logical inversion as occurring of a test mode to control the semiconductor device 200 to operate in the test mode, thereby incurring an error.
On the other hand, if the test-mode signal TEST1 is fixed at an H-level, due to occurring a test mode, the test execution circuit 202 allows the semiconductor device 200 to operate in a test mode. When the normal signal SIG1 rises from an L-level to an H-level in the normal operation, the test-mode signal line 203 is affected by the signal transition of the adjacent /SIG1 normal signal line 204 at the distal end. This causes a potential fluctuation of the test-mode signal TEST1, and if the range of potential fluctuation is large enough to cause a logical inversion of the test-mode signal TEST1 from an H-level to an L-level, as shown by a right dotted circle in FIG. 4, the test execution circuit 202 interprets the logical inversion as occurring of a normal mode to control the semiconductor device 200 to operate in the normal mode, thereby incurring an error.
In general, a typical semiconductor device employs a design configuration wherein the test-mode signal line used for transferring a test mode signal is disposed separately from the normal signal lines, thereby preventing the influence by the operation of the normal signal lines during a normal operation mode. In an alternative or in addition thereto, a shield line is interposed between the test-mode signal line and the normal signal lines, or a buffer is interposed at the interface between the high resistance first portion 203a and the low resistance second portion 203b of the test-mode signal line 203, or the vicinity of the test executing circuit 202 to suppress the fluctuation of the potential of test-mode signal line 203.
FIG. 5 shows an example for suppressing the level fluctuation of the test-mode signal line, as described above. In a portion of the semiconductor device 200a, a shield line 207 fixed at a specific potential, e.g. ground potential, is interposed between the low resistance second portion 203b of the TEST1 signal line 203 and the /SIG1 normal signal line 204. In another portion, a buffer 208 is interposed between the high resistance first portion 203a and another low resistance second portion 203c of the TEST1 signal line 203 or the vicinity thereof FIG. 6 is a waveform diagram showing operation of the semiconductor device 200a shown in FIG. 5. If /SIG1 normal signal line 204 changes the signal level thereof in the normal operation, node N23 of the adjacent shield line 207 may change the potential thereof in response to the influence by the transition noise from /SIG1 normal signal line 204. The potential of node N21 of TEST1 signal line 203 also fluctuates due to the influence by the potential fluctuation of /SIG1 normal signal line 204 and shield line 207; however, the range of potential fluctuation of /TEST1 signal line 203 is by far lower in FIG. 5 than in the case where the shield line 207 is not interposed between /SIG1 normal signal line 204 and /TEST1 signal line 203, as shown by a left dotted circle in FIG. 6. Thus, a logical inversion of/TEST1 signal line 203 does not occur whereby an erroneous operation can be avoided.
In the vicinity of input of the test execution circuit 202b, if /SIG1 normal signal line 204 changes the potential thereof in the normal operation, the potential of node N22 of the adjacent TEST1 signal line 203 fluctuates due to the transition noise of/SIG1 normal signal line 204. However, since node N22 of the low resistance second portion 203c drives the test execution circuit 202b, the range of potential fluctuation of node N22 is smaller in FIG. 5 compared to the case where the buffer 208 is not interposed, whereby erroneous operation can be avoided, as shown in the right dotted line in FIG. 6.
In the technique wherein the test-mode signal line is disposed separately from the normal signal lines as well as the technique using a shield line between the test-mode signal line and the normal signal lines, there is a problem that the layout design of the signal lines consumes a longer time length due to the extraction of each of the test-mode signal lines. There is also a risk wherein it is difficult to correctly extract all the test mode lines from the normal signal lines.
In the technique using a buffer between the high resistance first portion and the low resistance second portion of the test-mode signal line or in the vicinity of the test execution circuit, there is a problem that it is difficult to find a space sufficient for disposing the buffer in the very vicinity of the test execution circuit.